Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dti_inv
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00

Source File(s) :
/nfs_project/gemini/DV/mahmood/reg_sed/gemini/design/ip/dti/libs/dti_tm28hpcp_ddr4_phy/hdl/library/dti_tm28hpcp_l30_stdcells_10t_rev1p0p3.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst71.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst77.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst82.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst83.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst92.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst121.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst130.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst154.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst171.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst208.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst216.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst263.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst277.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst300.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst314.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst372.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst403.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst406.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst407.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst412.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst444.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst478.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst481.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst482.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst517.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst528.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst537.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst554.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst560.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst564.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst572.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst584.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst597.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst598.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst615.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst625.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst632.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst645.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst675.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst714.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst716.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst769.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst793.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst795.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst813.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst823.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst856.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst931.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst969.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst978.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst985.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1018.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1019.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1047.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1061.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1067.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1072.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1112.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1156.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1169.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1176.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1178.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1255.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1261.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1293.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1300.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1327.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1334.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1396.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1477.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1502.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1530.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1544.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1548.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1557.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1565.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1569.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1575.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1584.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1587.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1588.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1615.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1636.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1657.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1665.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1681.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1684.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1721.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1740.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1768.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1769.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1781.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1813.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1818.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1833.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1853.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1903.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1915.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1932.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1961.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1969.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1993.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1997.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2006.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2029.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2051.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2052.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2088.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2097.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2110.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2120.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2164.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2175.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2209.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2250.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2272.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2315.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2368.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2372.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2420.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2444.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2477.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2499.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2500.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2505.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2529.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2561.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2575.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2582.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2604.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2627.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2649.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2677.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2680.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2715.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2742.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2746.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2752.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2778.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2796.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2854.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2926.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2946.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2957.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2990.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2999.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3013.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3018.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3038.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3042.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3044.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3052.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3072.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3079.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3096.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3113.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3120.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3124.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3153.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3157.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3161.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3181.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3189.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3210.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3244.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3279.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3298.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3305.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3325.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3398.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3405.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3420.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3439.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3481.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3482.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3518.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3532.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3542.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3554.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3601.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3642.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3665.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3689.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3706.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3707.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3722.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3736.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3831.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3856.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3872.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3933.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3947.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3960.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3993.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4010.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4035.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4048.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4082.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4140.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4146.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4180.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4274.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4280.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4300.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4302.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4324.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4338.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4345.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4352.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4363.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4374.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4379.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4398.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4428.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4453.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4468.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4487.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4504.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4528.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4530.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4553.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4565.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4584.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4586.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4649.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4661.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4694.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4715.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4721.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4736.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4805.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4813.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4850.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4866.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4919.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4923.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4934.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4963.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5001.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5013.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5028.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5029.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5037.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5038.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5042.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5060.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5064.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5067.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5111.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5122.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5130.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5140.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5161.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5164.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5185.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5241.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5247.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5255.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5269.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5303.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5363.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5392.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5423.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5434.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5476.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5492.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5511.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5521.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5548.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5587.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5606.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5614.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5635.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5697.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5699.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5716.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5731.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5737.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5754.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5761.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5762.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5788.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5797.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5800.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5803.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5831.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5883.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5915.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5934.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5947.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5989.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6006.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6021.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6027.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6029.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6036.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6050.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6064.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6067.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6068.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6083.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6106.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6122.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6155.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6166.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6182.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6202.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6207.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6225.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6237.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6251.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6257.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6280.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6282.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6296.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6346.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6363.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6365.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6372.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6385.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6404.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6420.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6437.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6528.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6537.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6584.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6630.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6649.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6652.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6655.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6672.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6716.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6768.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6797.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6805.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6819.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6823.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6854.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6917.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6929.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6977.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6985.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6995.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7001.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7076.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7091.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7100.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7103.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7135.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7139.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7147.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7164.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7174.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7186.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7189.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7198.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7208.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7209.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7240.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7258.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7266.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7267.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7277.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7292.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7320.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7337.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7347.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7366.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7374.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7375.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7378.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7393.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7426.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7446.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7481.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7499.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7516.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7530.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7554.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7581.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7582.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7598.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7603.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7615.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7621.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7624.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7625.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7628.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7640.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7653.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7661.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7679.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7712.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7752.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7754.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7755.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7762.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7784.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7800.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7801.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7817.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7845.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7853.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7885.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7894.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7900.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7912.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7914.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7954.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7961.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7986.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8011.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8014.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8017.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8052.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8073.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8121.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8151.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8167.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8174.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8189.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8235.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8236.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8243.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8254.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8299.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8315.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8321.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8324.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8340.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8366.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8385.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8410.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8412.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8441.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8484.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8489.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8495.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8566.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8581.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8605.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8609.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8635.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8654.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8714.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8742.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8854.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8862.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8865.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8866.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8868.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8918.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8940.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8957.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9029.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9039.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9107.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9153.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9161.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9204.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9215.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9245.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9259.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9279.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9294.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9325.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9351.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9373.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9382.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9386.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9392.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9424.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9444.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9455.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9467.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9476.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9562.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9618.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9625.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9660.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9699.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9700.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9780.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9812.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9823.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9841.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9844.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9862.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9923.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9949.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9962.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9972.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10001.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10011.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10017.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10028.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10031.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10035.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10069.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10096.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10102.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10106.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10249.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10289.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10392.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10475.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10478.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10489.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10511.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10540.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10561.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10572.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10637.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10654.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10657.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10660.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10667.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10677.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10694.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10704.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10709.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10738.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10751.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10752.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10772.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10839.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10850.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10851.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10873.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10885.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10915.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10918.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10931.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10964.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10971.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10978.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11028.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11052.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11077.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11089.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11125.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11141.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11161.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11193.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11200.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11207.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11209.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11223.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11250.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11252.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11261.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11284.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11285.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11312.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11316.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11329.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11331.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11377.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11381.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11382.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11387.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11394.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11405.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11406.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11407.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11493.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11506.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11517.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11532.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11538.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11569.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11614.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11616.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11617.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11620.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11629.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11634.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11648.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11659.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11667.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11672.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11684.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11692.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11701.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11750.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11755.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11756.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11757.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11768.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11770.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11782.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11796.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11797.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11803.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11807.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11810.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11824.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11827.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11833.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11837.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11846.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11862.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11912.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11927.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11935.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12010.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12033.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12054.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12084.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12102.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12106.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12120.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12150.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12175.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12178.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12197.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12201.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12202.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12219.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12265.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12269.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12293.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12307.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12318.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12334.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12358.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12364.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12401.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12425.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12431.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12450.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12454.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12464.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12475.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12477.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12482.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12483.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12494.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12506.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12542.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12548.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12612.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12618.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12636.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12643.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12669.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12702.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12756.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12758.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12761.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12763.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12764.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12785.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12793.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12824.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12828.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12851.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12866.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12874.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12883.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12898.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12903.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12958.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12973.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13015.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13019.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13057.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13062.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13064.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13068.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13072.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13081.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13091.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13112.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13137.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13140.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13175.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13193.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13203.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13204.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13207.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13219.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13241.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13242.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13269.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13274.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13298.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13311.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13324.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13345.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13369.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13371.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13376.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13379.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13472.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13473.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13478.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13494.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13497.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13500.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13514.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13537.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13545.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13598.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13636.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13642.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13691.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13712.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13714.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13727.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13739.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13750.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13789.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13831.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13895.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13897.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13898.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13932.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13938.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13948.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13949.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13958.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13988.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13993.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14008.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14011.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14041.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14045.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14047.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14058.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14068.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14069.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14070.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14079.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14109.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14110.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14112.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14144.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14147.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14151.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14153.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14158.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14183.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14210.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14216.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14224.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14292.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14338.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14346.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14358.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14377.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14402.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14423.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14447.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14450.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14483.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14493.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14518.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14519.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14548.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14566.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14570.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14574.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14575.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14587.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14589.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14605.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14669.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14672.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14686.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14700.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14729.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14737.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14746.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14763.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14765.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14780.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14782.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14794.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14803.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14818.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14855.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14868.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14889.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14898.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14907.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14963.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14989.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14999.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15014.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15015.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15021.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15027.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15031.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15071.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15088.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15124.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15125.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15142.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15151.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15157.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15161.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15164.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15183.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15203.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15204.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15236.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15245.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15249.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15250.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15329.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15334.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15349.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15365.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15379.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15386.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15396.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15402.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15406.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15407.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15434.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15437.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15454.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15483.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15493.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15514.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15554.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15557.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15561.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15585.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15592.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15597.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15606.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15616.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15624.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15636.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15653.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15660.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15778.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15821.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15872.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15876.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15902.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15914.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15918.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15944.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15950.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15981.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15989.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15993.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15994.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16001.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16004.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16016.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16036.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16038.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16043.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16050.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16059.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16078.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16111.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16169.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16184.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16206.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16237.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16240.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16251.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16266.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16287.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16288.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16334.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16374.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16400.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16411.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16416.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16446.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16459.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16475.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16482.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16508.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16521.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16539.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16579.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16603.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16634.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16683.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16707.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16731.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16762.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16787.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16795.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16827.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16845.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16858.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16880.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16894.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16898.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16900.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16952.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16953.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16955.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16980.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16985.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16986.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17007.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17068.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17075.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17094.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17103.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17112.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17133.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17163.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17164.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17176.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17188.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17238.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17258.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17277.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17284.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17303.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17307.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17315.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17320.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17373.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17385.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17431.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17437.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17455.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17484.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17517.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17529.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17542.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17564.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17572.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17589.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17615.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17630.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17640.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17680.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17681.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17697.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17722.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17795.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17818.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17830.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17834.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17848.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17856.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17860.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17864.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17938.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17939.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17972.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17990.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17992.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18008.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18010.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18037.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18052.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18062.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18065.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18088.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18096.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18154.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18155.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18158.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18165.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18174.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18178.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18204.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18242.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18260.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18342.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18377.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18416.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18428.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18431.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18453.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18463.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18468.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18479.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18481.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18490.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18529.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18532.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18581.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18583.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18594.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18613.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18628.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18689.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18694.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18742.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18765.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18782.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18783.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18796.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18798.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18824.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18854.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18856.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18861.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18874.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18897.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18898.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18905.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18907.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18910.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18932.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18938.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18954.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18960.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18972.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18985.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19049.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19065.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19069.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19071.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19102.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19108.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19125.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19130.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19132.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19141.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19152.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19157.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19166.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19251.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19253.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19255.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19280.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19289.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19303.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19307.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19327.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19330.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19345.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19405.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19476.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19502.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19509.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19510.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19521.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19528.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19544.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19569.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19588.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19626.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19645.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19691.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19698.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19712.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19737.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19789.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19849.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19852.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19855.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19856.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19883.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19900.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19926.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19949.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19962.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19966.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20016.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20017.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20028.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20045.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20054.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20094.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20110.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20142.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20169.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20178.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20183.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20191.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20236.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20237.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20245.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20258.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20299.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20336.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20342.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20364.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20366.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20374.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20377.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20391.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20402.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20403.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20450.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20457.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20472.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20475.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20482.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20518.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20533.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20583.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20587.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20606.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20636.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20637.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20667.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20671.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20676.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20677.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20744.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20749.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20772.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20782.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20787.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20850.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20857.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20873.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20917.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20933.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20935.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20946.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20948.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20956.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20957.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21000.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21071.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21083.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21108.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21119.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21122.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21135.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21150.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21155.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21216.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21220.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21228.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21242.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21258.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21271.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21294.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21309.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21336.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21340.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21346.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21410.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21423.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21448.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21492.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21517.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21554.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21556.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21558.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21602.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21648.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21657.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21663.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21695.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21734.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21753.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21756.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21761.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21762.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21805.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21816.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21851.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21870.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21877.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21900.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21922.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21929.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21932.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21941.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21958.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21977.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21994.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21999.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22028.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22032.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22064.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22073.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22077.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22086.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22110.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22118.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22121.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22145.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22157.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22188.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22207.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22219.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22220.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22235.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22239.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22259.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22281.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22305.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22314.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22316.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22334.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22351.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22370.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22386.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22403.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22453.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22468.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22470.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22472.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22475.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22479.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22484.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22499.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22545.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22551.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22558.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22602.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22606.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22609.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22619.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22629.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22634.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22642.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22652.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22676.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22688.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22729.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22764.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22765.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22787.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22788.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22797.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22828.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22854.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22876.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22897.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22918.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22946.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22966.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22970.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22988.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22990.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23017.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23045.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23057.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23069.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23077.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23078.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23081.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23100.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23111.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23112.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23117.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23142.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23186.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23220.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23266.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23313.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23318.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23358.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23364.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23381.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23396.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23401.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23428.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23435.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23442.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23449.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23454.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23566.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23577.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23589.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23615.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23654.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23676.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23683.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23757.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23759.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23797.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23798.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23811.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23825.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23850.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23915.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23947.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23961.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24022.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24057.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24116.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24125.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24146.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24156.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24178.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24184.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24210.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24240.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24248.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24249.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24263.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24264.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24289.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24329.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24337.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24346.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24378.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24421.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24425.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24446.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24492.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24497.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24506.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24537.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24598.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24600.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24602.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24625.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24635.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24651.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24653.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24659.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24664.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24689.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24700.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24779.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24781.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24783.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24796.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24817.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24833.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24880.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24894.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24947.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24952.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24953.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24958.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24963.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24966.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25037.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25072.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25117.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25131.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25134.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25142.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25180.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25188.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25197.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25220.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25241.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25243.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25257.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25265.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25287.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25302.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25313.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25347.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25364.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25371.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25382.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25426.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25439.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25444.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25467.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25494.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25503.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25519.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25530.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25545.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25574.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25619.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25621.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25628.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25630.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25665.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25695.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25699.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25706.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25718.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25733.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25736.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25756.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25772.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25785.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25789.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25819.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25826.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25874.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25889.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25895.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25909.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25918.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25920.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25934.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25939.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25944.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25969.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26014.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26019.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26050.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26053.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26091.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26106.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26123.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26133.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26147.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26166.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26180.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26185.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26219.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26222.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26260.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26279.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26283.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26317.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26324.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26347.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26402.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26409.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26437.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26454.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26467.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26478.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26479.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26495.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26523.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26532.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26620.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26650.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26693.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26701.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26742.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26750.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26762.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26782.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26817.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26821.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26823.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26824.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26830.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26864.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26869.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26877.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26881.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26882.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26902.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26933.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26947.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26948.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26952.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26980.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27004.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27054.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27064.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27065.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27068.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27073.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27096.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27113.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27117.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27131.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27158.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27165.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27204.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27221.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27235.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27244.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27271.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27283.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27287.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27299.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27305.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27320.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27352.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27365.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27366.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27371.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27381.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27387.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27394.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27409.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27420.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27431.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27444.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27458.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27464.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27466.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27483.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27484.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27497.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27534.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27535.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27538.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27545.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27551.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27553.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27576.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27597.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27632.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27643.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27671.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27679.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27685.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27686.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27739.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27750.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27772.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27811.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27813.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27834.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27853.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27861.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27900.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27902.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27903.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27907.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27974.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27989.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28031.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28047.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28048.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28049.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28080.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28154.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28160.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28176.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28181.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28191.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28207.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28216.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28220.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28224.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28241.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28272.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28292.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28309.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28335.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28370.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28385.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28406.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28420.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28428.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28431.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28437.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28447.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28455.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28459.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28461.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28490.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28499.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28506.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28509.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28543.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28551.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28557.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28569.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28576.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28637.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28684.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28691.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28698.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28703.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28716.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28725.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28751.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28753.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28761.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28798.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28820.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28846.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28849.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28851.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28889.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28890.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28895.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28921.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28946.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28958.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28963.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28985.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28986.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28993.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29000.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29017.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29033.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29048.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29049.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29056.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29058.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29062.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29065.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29071.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29086.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29087.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29088.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29132.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29134.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29181.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29185.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29207.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29208.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29225.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29270.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29289.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29298.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29305.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29342.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29347.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29364.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29370.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29397.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29407.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29424.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29428.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29436.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29457.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29472.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29487.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29511.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29545.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29566.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29590.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29621.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29622.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29646.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29661.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29714.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29716.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29749.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29769.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29786.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29789.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29793.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29835.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29852.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29863.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29874.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29875.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29917.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29919.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29927.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29946.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29947.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29983.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30001.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30010.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30014.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30023.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30032.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30036.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30043.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30054.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30072.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30086.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30091.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30107.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30122.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30135.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30153.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30154.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30244.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30257.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30273.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30279.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30288.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30312.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30343.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30392.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30427.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30448.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30494.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30495.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30497.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30569.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30589.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30597.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30601.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30609.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30642.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30643.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30681.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30682.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30695.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30710.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30729.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30733.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30765.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30781.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30806.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30821.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30852.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30885.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30904.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30906.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30911.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30914.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30927.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30931.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30964.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30966.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30972.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30983.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31016.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31049.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31061.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31088.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31102.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31110.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31117.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31133.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31155.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31156.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31174.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31195.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31205.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31215.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31254.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31260.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31265.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31271.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31294.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31321.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31324.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31331.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31346.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31376.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31439.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31447.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31461.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31494.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31510.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31592.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31601.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31646.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31661.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31665.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31667.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31680.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31694.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31703.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31712.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31723.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31739.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31760.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31772.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31825.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31854.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31872.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31875.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31880.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31933.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31945.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31962.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31970.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31971.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31980.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31992.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32006.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32007.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32078.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32080.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32082.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32107.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32117.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32164.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32252.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32267.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32269.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32277.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32282.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32285.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32292.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32296.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32297.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32300.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32337.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32340.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32354.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32369.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32446.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32455.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32457.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32540.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32547.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32553.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32561.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32581.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32625.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32648.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32650.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32666.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32671.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32673.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32676.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32686.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32691.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32700.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32733.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32739.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32746.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32799.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32832.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32837.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32838.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32843.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32845.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32847.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32851.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32856.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32864.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32865.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32879.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32920.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32956.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32969.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32977.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32995.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33023.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33045.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33120.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33136.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33172.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33183.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33186.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33226.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33227.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33242.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33263.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33267.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33293.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33307.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33318.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33349.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33351.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33373.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33392.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33409.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33425.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33442.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33448.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33449.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33453.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33454.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33464.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33465.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33478.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33519.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33525.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33538.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33553.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33574.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33579.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33612.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33617.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33618.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33619.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33620.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33624.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33643.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33649.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33661.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33689.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33695.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33709.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33727.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33733.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33736.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33737.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33755.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33764.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33790.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33800.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33827.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33837.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33841.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33845.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33852.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33859.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33863.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33945.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33948.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33955.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33969.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33983.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34018.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34044.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34049.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34050.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34055.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34059.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34081.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34118.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34130.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34142.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34166.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst513.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst974.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1388.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1415.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2788.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4557.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7361.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8093.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8668.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9075.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9791.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10258.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10596.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11301.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst513.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6498.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6921.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8480.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8668.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst513.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6498.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6921.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8480.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8668.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst513.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst974.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6498.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6921.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7361.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8480.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10596.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11301.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst513.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst513.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst513.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst974.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1388.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6498.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7361.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8480.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9075.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10596.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11301.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst53.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst58.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst82.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst104.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst135.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst182.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst205.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst214.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst235.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst290.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst322.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst323.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst392.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst422.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst440.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst496.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst505.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst513.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst520.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst536.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst563.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst566.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst595.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst650.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst713.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst743.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst748.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst782.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst796.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst797.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst812.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst815.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst840.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst852.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst886.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst894.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst897.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst913.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst917.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst920.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst931.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst5.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst7.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst20.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst23.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst31.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst32.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst38.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst50.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst69.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst72.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst76.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst83.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst101.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst118.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst126.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst132.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst143.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst148.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst161.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst168.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst171.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst186.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst198.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst199.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst212.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst225.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst240.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst253.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst255.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst256.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst266.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst267.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst275.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst280.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst286.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst289.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst297.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst298.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst311.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst314.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst317.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst320.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst329.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst332.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst341.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst356.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst359.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst361.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst367.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst386.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst416.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst417.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst422.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst966.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst974.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst979.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst980.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst982.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1020.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1051.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1074.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1090.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1262.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1288.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1306.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1307.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1328.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1345.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1372.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1388.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1415.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1429.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1433.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1469.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1507.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1535.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1565.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1569.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1598.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1670.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1674.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1709.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1793.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1830.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1858.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1956.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1987.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2002.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2026.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2034.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2060.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2080.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2098.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2268.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2395.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2396.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2397.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2439.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2445.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2470.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2471.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2496.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2587.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2610.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2624.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2658.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2680.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2732.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2742.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2744.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2748.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2767.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2771.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2788.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2790.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2869.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2887.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2936.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2941.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2981.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3003.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3034.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3054.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3073.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3120.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3163.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3173.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3182.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3191.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3199.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3212.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3232.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3234.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3245.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3263.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3278.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3305.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3332.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3342.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3353.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3430.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3526.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3543.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3546.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3576.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3682.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3708.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3728.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3770.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3777.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3791.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3870.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3887.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3896.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3919.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3925.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3942.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3967.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4040.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4110.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4113.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4129.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4134.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4143.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4159.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4187.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4233.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4236.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4246.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4257.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4281.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4292.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4295.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4308.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4327.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4346.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4356.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4388.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4421.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4486.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4557.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4578.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4580.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4581.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4591.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4627.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4719.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4720.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4901.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4902.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4926.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4954.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4960.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5048.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5070.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5092.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5098.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5116.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5117.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5139.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5166.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5179.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5213.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5291.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5294.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5321.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5336.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5344.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5390.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5508.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5568.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5593.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5631.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5644.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5646.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5666.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5721.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5736.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5771.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5775.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5776.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5802.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5822.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5836.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5842.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5847.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5911.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5934.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5965.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5999.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6043.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6047.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6066.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6093.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6109.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6115.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6125.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6144.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6159.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6160.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6174.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6177.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6196.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6199.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6200.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6214.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6230.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6231.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6281.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6303.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6304.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6317.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6322.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6326.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6341.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6347.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6352.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6360.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6362.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6452.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6457.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6458.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6461.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6472.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6498.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6509.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6512.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6520.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6526.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6550.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6584.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6601.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6604.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6608.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6637.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6689.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6693.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6695.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6711.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6723.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6772.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6787.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6814.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6824.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6829.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6836.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6845.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6846.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6891.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6893.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6916.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6921.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6988.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6990.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7005.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7021.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7024.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7045.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7063.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7147.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7149.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7162.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7175.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7216.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7239.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7242.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7252.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7268.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7284.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7326.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7334.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7344.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7353.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7357.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7361.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7411.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7419.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7512.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7522.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7549.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7594.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7595.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7638.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7639.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7656.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7660.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7696.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7745.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7758.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7765.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7775.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7778.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7794.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7807.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7815.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7838.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7842.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7871.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7874.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7876.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7884.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7888.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7892.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7924.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7929.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7947.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7959.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7998.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8046.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8093.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8102.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8146.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8149.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8172.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8176.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8184.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8202.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8227.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8229.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8256.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8276.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8316.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8339.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8362.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8366.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8368.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8382.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8384.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8441.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8456.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8479.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8480.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8506.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8527.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8531.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8532.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8533.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8555.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8562.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8570.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8571.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8645.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8668.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8672.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8720.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8735.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8741.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8788.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8805.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8867.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8872.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8878.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8899.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8928.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8976.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8989.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9008.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9022.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9056.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9075.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9085.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9089.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9107.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9138.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9152.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9180.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9190.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9207.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9217.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9238.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9268.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9278.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9283.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9348.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9350.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9367.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9383.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9413.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9414.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9418.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9454.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9469.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9470.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9490.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9524.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9540.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9567.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9579.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9582.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9586.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9607.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9608.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9613.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9641.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9647.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9662.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9700.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9753.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9773.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9791.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9804.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9810.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9832.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9833.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9861.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9880.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9921.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9955.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9975.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9982.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9996.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9997.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10044.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10086.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10095.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10133.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10189.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10258.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10269.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10319.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10324.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10331.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10387.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10389.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10408.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10427.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10432.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10455.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10488.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10592.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10596.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10609.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10611.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10623.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10643.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10656.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10686.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10693.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10706.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10726.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10735.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10776.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10792.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10800.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10835.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10867.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10879.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10885.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10886.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10889.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10891.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10908.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10925.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10932.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10936.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10937.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10943.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10944.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10964.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10967.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10984.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10991.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10997.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11002.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11009.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11095.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11114.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11127.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11141.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11158.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11185.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11188.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11211.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11238.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11264.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11293.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11301.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11308.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11338.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11349.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11369.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11390.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11404.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11412.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11414.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11418.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11438.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11443.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11451.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11466.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11497.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11534.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11541.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11552.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11558.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11559.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11563.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11568.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11591.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11616.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11638.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11661.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11677.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11679.xdti_28hc_10t_30_inv 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11685.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11694.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11711.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11728.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11774.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11803.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11809.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11849.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11864.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11871.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11881.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11910.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i2.x1i46.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i2.x1i52.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i2.x1i56.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i2.x1i68.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i2.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i17.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i24.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i30.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i36.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i68.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i81.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i6.x1i91.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i14.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11968.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11972.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11981.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12020.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12025.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12033.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12036.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12055.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12059.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12060.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12062.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12071.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12076.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12121.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12128.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12129.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12153.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12192.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12211.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12229.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12231.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12272.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12310.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12325.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12337.xdti_28hc_10t_30_inv 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12339.xdti_28hc_10t_30_inv 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12341.xdti_28hc_10t_30_inv 50.00 50.00

Toggle Coverage for Module : dti_inv
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 8 4 50.00
Total Bits 0->1 4 2 50.00
Total Bits 1->0 4 2 50.00

Ports 4 2 50.00
Port Bits 8 4 50.00
Port Bits 0->1 4 2 50.00
Port Bits 1->0 4 2 50.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
A Yes Yes Yes INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%